RC22504A Description
The RC22504A is a small, low-power timing ponent designed to be placed immediately adjacent to a PHY, switch, ASIC or FPGA that requires several reference clocks with jitter performance less than 100fs (max). The RC22504A can act as a frequency synthesizer to locally generate the reference clock or as a DCO for frequency margining or OTN clock applications. The device is a member of Renesas' highperformance...
RC22504A Key Features
- Jitter as low as 64 fs RMS maximum (10kHz to 20MHz)
- PLL core consists of fractional-feedback Analog PLL (APLL)
- Programmable status output
- 4 differential / 8 LVCMOS outputs
- Supports up to 1MHz I2C or up to 20MHz SPI serial processor port
- Can configure itself automatically after reset via internal customer-definable One-Time Programmable (OTP) memory with u
- 4 × 4 mm 24-QFN package
- 8 1.1 Document Conventions
- 8 1.1.1 Signal Notation
- 8 1.1.2 Object Size Notation
RC22504A Applications
- Reference clock generator for 100Gbps / 400Gbps PHYs or switches
- Adjustable OTN clock reference for OTU3 / OTU4 mappers
- Reference clock for programmable FiberOptic Modules
- Jitter as low as 64 fs RMS maximum (10kHz to 20MHz)