Description
The RC22504A is a small, low-power timing component designed to be placed immediately adjacent to a PHY, switch, ASIC or FPGA that requires several reference clocks with jitter performance less than 100fs (max).
Features
- Jitter as low as 64 fs RMS maximum (10kHz to 20MHz).
- PLL core consists of fractional-feedback Analog PLL (APLL)
○ Operates from a 25MHz to 80MHz crystal or XO
○ APLL frequency independent of input / crystal frequency
○ Operates as a frequency synthesizer or Digitally Controlled Oscillator (DCO)
○ DCO has tuning granularity of < 1ppb.
- Programmable status output.
- 4 differential / 8 LVCMOS outputs
○ Any frequency from 10MHz to 1GHz (180MHz for LVCMOS)
○ Programm.
RC22504A Datasheet
