RC31008B Datasheet PDF - Renesas VersaClock 7 Programmable Jitter Attenuator Specs

RC31008B - VersaClock 7 Programmable Jitter Attenuator

Datasheet Summary

Description

The RC310xxB are high-performance programmable jitter attenuators with network synchronization capabilities.

The devices support JEDEC JESD204B/C for converter synchronization, and SyncE for network-based synchronization.

Features

169fs RMS phase jitter at 156.25MHz (typ. ).
PCIe® Gen7 Common Clock jitter: 8fs RMS (typ. ).
Compliant with ITU-T G.8262 and G.8262.1 for synchronous Ethernet Equipment Clock (EEC/eEEC).
Jitter attenuation with programmable loop bandwidth from 0.1Hz to 12kHz.
1kHz to 650MHz LVDS/LP-HCSL outputs.
1kHz to 200MHz LVCMOS outputs.
Simple AC-coupling to LVPECL and CML.
Integrated 100 and 85 LP-HCSL terminations.
JESD204B/C support on differential or singl.

Datasheet Details

Part number	RC31008B
Manufacturer	Renesas
File Size	1.99 MB
Description	VersaClock 7 Programmable Jitter Attenuator
Datasheet	RC31008B Datasheet
Additional preview pages of the RC31008B datasheet.

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Full PDF Text Transcription

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RC310xxB VersaClock 7 Programmable Jitter Attenuator Family Datasheet Description The RC310xxB are high-performance programmable jitter attenuators with network synchronization capabilities. The devices support JEDEC JESD204B/C for converter synchronization, and SyncE for network-based synchronization. The RC310xxB are ideal for driving converter circuits in wire-line infrastructure, data center equipment, and instrumentation applications. Applications ▪ Switches / Routers ▪ Synchronous Ethernet (SyncE) equipment ▪ Telecom Time Slave Clock (T-TSC) equipment ▪ Jitter attenuation for 10 / 25 / 40 / 100 / 200 / 400 Gbps Ethernet PHYs or Switches ▪ Small Cell for 4.5G and 5G Features ▪ 169fs RMS phase jitter at 156.25MHz (typ.) ▪ PCIe® Gen7 Common Clock jitter: 8fs RMS (typ.

Published: Jan 9, 2025 |