Minimum instruction execution time: Can be changed
from high speed (0.04167 s: @ 24 MHz operation with high-speed on-chip oscillator) to ultra-low speed (66.6 s: @ 15 kHz operation with low-speed on-chip oscillator clock).
Multiply/divide/multiply & accumulate instructions are suppo.
Full PDF Text Transcription for RL78I1D (Reference)
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RL78I1D. For precise diagrams, and layout, please refer to the original PDF.
RL78/I1D RENESAS MCU 1. OUTLINE 1.1 Features Ultra-low power consumption technology • VDD = 1.6 V to 3.6 V • HALT mode • STOP mode • SNOOZE mode RL78 CPU core • CISC arch...
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3.6 V • HALT mode • STOP mode • SNOOZE mode RL78 CPU core • CISC architecture with 3-stage pipeline • Minimum instruction execution time: Can be changed from high speed (0.04167 s: @ 24 MHz operation with high-speed on-chip oscillator) to ultra-low speed (66.6 s: @ 15 kHz operation with low-speed on-chip oscillator clock) • Multiply/divide/multiply & accumulate instructions are supported. • Address space: 1 MB • General-purpose registers: (8-bit register 8) 4 banks • On-chip RAM: 0.
RL78I1D Datasheet
