MS90C104 Datasheet | Ruimeng

Description The MS90C104 receiver is designed to support pixel data transmission between Host and Flat Panel Display from NTSC up to SXGA resolutions. The MS90C104 converts the LVDS data streams back into 35bits of CMOS/TTL data with the choice of the rising edge or falling edge clock for the convenience with a variety of LCD panel controllers. At a transmit clock frequency of 175Mhz, 30bits of GRB data and 5bits of timing and control data (HSYNC,VSYCN,DE,CNTL1,CNTL2) are transmitted at an effective rate of 1225Mbps per LVDS channel. Using a 175MHz clock, the data throughput is 765.6Mbytes/sec. Features - Clock range：8-175MHz - Narrow bus reduces cable size - Single 3.3V supply - Power-down Mode - Supports VGA、SVGA、XGA、SXGA - Up to 6.125Gbps throughput - Up to 765.6Megabytes/sec bandwidth - PLL requires no external ponents - patible with TIA/EIA-644 LVDS standard - TQFP64 Package Hangzhou Ruimeng Technology Co.,LTD Http: .relmon. -- 1 - - Pin Diagram Pin Description Pin Name RL0+,RL0RL1+, RL1RL2+, RL2RL3+, RL3RL4+, RL4RCLK+, RCLK- Pin No. 49, 50 51, 52 54, 55 59, 60 61，62 56, 57 Rx OUT0 ~ Rx OUT6 Rx OUT7 ~ Rx OUT13 Rx OUT14 ~ Rx OUT20 Rx OUT21 ~ Rx OUT27 47,46,45,43,42,20,41 40,39,38,19,18,36,35 34,33,17,15,32,29,28 27,26,14,25,24,22,21 I/O LVDS IN LVDS IN LVDS IN LVDS IN LVDS IN LVDS IN OUT OUT OUT OUT Description LVDS differential data inputs LVDS differential clock inputs TTL level data outputs. This includes：10 RED,10 GREEN,10 BLUE,5 control lines （HSYNC，VSYNC，DE， Hangzhou Ruimeng Technology Co.,LTD Http: .relmon. -- 2 - - Rx OUT28 ~ Rx OUT34 CLKOUT 13,12,11,10,8,7,6 31 R_FB TEST Vcc GND LVDS Vcc LVDS GND PLL Vcc PLL...