SST34HF3244C Overview
Key Features
- Dual-Bank Architecture for Concurrent Read/Write Operation – 32 Mbit Top Sector Protection – 8 Mbit + 24 Mbit
- SRAM Organization: – 4 Mbit: 256K x16
- Single 2.7-3.3V Read and Write Operations
- Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention
- Low Power Consumption: – Active Current: 25 mA (typical) – Standby Current: 20 µA (typical)
- Hardware Sector Protection (WP#) – Protects 8 KWord in the smaller bank by holding WP# low and unprotects by holding WP# high
- Hardware Reset Pin (RST#) – Resets the internal state machine to reading data array
- Sector-Erase Capability – Uniform 2 KWord sectors
- Flash Chip-Erase Capability
- Block-Erase Capability – Uniform 32 KWord blocks
