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M68Z128 - 5V / 1 Mbit 128Kb x8 Low Power SRAM with Output Enable

General Description

The M68Z128 is a 1 Mbit (1,048,576 bit) CMOS SRAM, organized as 131,072 words by 8 bits.

Key Features

  • fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 5V ±10% supply, and all inputs and outputs are TTL compatible. A0-A16 VCC 17 8 DQ0-DQ7 Table 1. Signal Names A0-A16 DQ0-DQ7 E1 E2 G W VCC VSS NC March 2000 Address Inputs Data Input/Output Chip Enable 1 Chip Enable 2 Output Enable Write Enable Supply Voltage Ground Not Connected Internally 1/12 W E1 E2 G M68Z128 VSS AI00647 M68Z128 Table 2. Absolute Maximu.

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Other Datasheets by STMicroelectronics

Part Number Description
M68Z128W 3V / 1 Mbit 128Kb x8 Low Power SRAM with Output Enable
M68Z512 4 Mbit 512Kb x8 Low Power SRAM with Output Enable
M68AF031A 256 Kbit (32K x 8) 5.0V Asynchronous SRAM
M68AF127B 1Mbit 128K x8 / 5V Asynchronous SRAM
M68AF511A 4 Mbit (512K x8) / 5V Asynchronous SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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M68Z128 5V, 1 Mbit (128Kb x8) Low Power SRAM with Output Enable s ULTRA LOW DATA RETENTION CURRENT – 10nA (typical) – 2.0µA (max) s s OPERATION VOLTAGE: 5V ±10% 128Kb x 8 VERY FAST SRAM with OUTPUT ENABLE EQUAL CYCLE and ACCESS TIMES: 55ns LOW VCC DATA RETENTION: 2V TRI-STATE COMMON I/O LOW ACTIVE and STANDBY POWER AUTOMATIC POWER-DOWN WHEN DESELECTED INTENDED FOR USE WITH ST ZEROPOWER® AND TIMEKEEPER ® CONTROLLERS Figure 1. Logic Diagram TSOP32 (N) 8 x 20mm s s s s s s DESCRIPTION The M68Z128 is a 1 Mbit (1,048,576 bit) CMOS SRAM, organized as 131,072 words by 8 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 5V ±10% supply, and all inputs and outputs are TTL compatible.