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M68Z128W - 3V / 1 Mbit 128Kb x8 Low Power SRAM with Output Enable

General Description

The M68Z128W is a 1 Mbit (1,048,576 bit) Fast CMOS SRAM, organized as 131,072 words by 8 bits.

Key Features

  • fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 3.0V (+0.6V /.
  • 0.3V) supply, and all inputs and outputs are TTL compatible. This device has an automatic power-down feature, reducing the power consumption by over 99% when deselected. The M68Z128W is available in the standard 450mil-wide TSOP type 1 package. Figure 1. Logic Diagram VCC 17 A0-A16 8 DQ0-DQ7 Table 1. Signal Names A0-A16 DQ0-DQ7 E1 E2 G.

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Other Datasheets by STMicroelectronics

Part Number Description
M68Z128 5V / 1 Mbit 128Kb x8 Low Power SRAM with Output Enable
M68Z512 4 Mbit 512Kb x8 Low Power SRAM with Output Enable
M68AF031A 256 Kbit (32K x 8) 5.0V Asynchronous SRAM
M68AF127B 1Mbit 128K x8 / 5V Asynchronous SRAM
M68AF511A 4 Mbit (512K x8) / 5V Asynchronous SRAM

Full PDF Text Transcription (Reference)

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M68Z128W 3V, 1 Mbit (128Kb x8) Low Power SRAM with Output Enable s s LOW VOLTAGE: 3.0V (+0.6V / –0.3V) 128Kb x 8 LOW POWER SRAM with OUTPUT ENABLE EQUAL CYCLE and ACCESS TIMES: 70ns LOW VCC DATA RETENTION: 1.4V TRI-STATE COMMON I/O LOW ACTIVE and STANDBY POWER INTENDED for USE with ST ZEROPOWER® and TIMEKEEPER® CONTROLLERS TSOP32 (N) 8 x 20mm s s s s s DESCRIPTION The M68Z128W is a 1 Mbit (1,048,576 bit) Fast CMOS SRAM, organized as 131,072 words by 8 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 3.0V (+0.6V / –0.3V) supply, and all inputs and outputs are TTL compatible.