STB5105 Datasheet | STMicroelectronics

DESCRIPTION LQFP216 or 23 mm x 23 mm BGA package. STMicroelectronics sets a new standard for perfomance, price and integration in the single chip MPEG-2 set-top box decoder market with the introduction of the STM5105. This highly integrated solution targets mass market STBs, offers increased performance over earlier devices, and includes many Features to further reduce costs, including a unified memory architecture. The STM5105 Features the ST20 CPU that is standard across the OMEGA range but boosts the clock speed to 200 MHz which, when bined with the 2D graphics engine, gives the new device outstanding graphics performances. Targeting low-cost, single tuner STB applications, the STM5105’s DDR memory interface both reduces system costs and minimises overall xxxx system latency, ensuring the new device can . support the most demanding interactive TV Data Shee applications and middlewares. The integration of VCXO and audio DACs ensures that manufacturers using the STM5105 cut their bill of materials and significantly simplify board design and assembly. Figure 1. STM5105 low-cost interactive set-top box stream in STV0299 and STB6000 STV0299 tuner and STB6000 tuner STV0297 QAM demodulator STV0297 + tuner QAM demodulator + tuner DRAM IR RX/TX Audio buffer OR STM5105 Video buffer . March 2005 STV0360 COFDM STV0360 + tuner COFDM + tuner Transport Smart card NOR Flash Rev. 1 1/3 . Data Sheet 4 U . .. STM5105 Features s Enhanced ST20 32-bit VL-RISC CPU - 200 MHz, single cycle cache, 4 Kbyte instruction cache, 4 Kbyte data cache, 2 Kbyte SRAM s s PAL/NTSC/SECAM encoder - RGB, CVBS, Y/C and YUV outputs with four 10-bit DAC outputs. RGB/CVBS or YUV/CVBS or YC/CVBS - Encoding of CGMS, Teletext, WSS, VPS, close caption Unified memory interface - Up to133 MHz,16-bit wide DDR interface s Audio subsystem - MPEG-1 layers I/II - Simultaneous MPEG audio decode and output of Dolby streams on S/PDIF - IEC958/IEC1937 digital audio output interface - Integrated stereo audio...