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STSMIA832 - standard mobile imaging architecture (SMIA) decoder deserializer

Description

The STSMIA832 receiver converts the subLVDS clock/datastream (up to 650 Mbps throughput bandwidth) back into parallel 8 bits of CMOS/LVTTL.

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Datasheet Details

Part number STSMIA832
Manufacturer STMicroelectronics
File Size 454.09 KB
Description standard mobile imaging architecture (SMIA) decoder deserializer
Datasheet download datasheet STSMIA832 Datasheet

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www.DataSheet4U.com STSMIA832 1.8V/2.8V High speed dual differential line receivers, standard mobile imaging architecture (SMIA) decoder deserializer Feature summary s Sub-low voltage differential signaling inputs: VID = 100mV MIN. with RT = 100Ω, CL = 10pF High signaling rate: fIN = 650 Mbps MAX (D+,D-,STRB+,STRB-) fOUT = 82 MHz MAX (CLK) fOUT = 82 Mbps MAX (for each data line D1-D8) Very high speed strobe to clock: tpLH~tpHL=5.2ns (TYP) at VDD=2.8V; VL=1.8V Operating voltage range: VDD(OPR) = 2.65V to 3.6V VL(OPR) =1.65V to 1.95V Symmetrical output impedance (D1-D8, HSYNC, V-SYNC, CLK): IIOHI=IOL=4mA (MIN) at VDD=2.65V;VL=1.
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