STSMIA832 Datasheet | STMicroelectronics

.. 1.8V/2.8V High speed dual differential line receivers, standard mobile imaging architecture (SMIA) decoder deserializer Feature summary s Sub-low voltage differential signaling inputs: VID = 100m V MIN. with RT = 100Ω, CL = 10p F High signaling rate: f IN = 650 Mbps MAX (D+,D-,STRB+,STRB-) f OUT = 82 MHz MAX (CLK) f OUT = 82 Mbps MAX (for each data line D1-D8) Very high speed strobe to clock: tp LH~tp HL=5.2ns (TYP) at VDD=2.8V; VL=1.8V Operating voltage range: VDD(OPR) = 2.65V to 3.6V VL(OPR) =1.65V to 1.95V Symmetrical output impedance (D1-D8, HSYNC, V-SYNC, CLK): IIOHI=IOL=4m A (MIN) at VDD=2.65V;VL=1.8V Low power dissipation (DISABLED: EN=Gnd): ISOFF = IDD + IL = 10 µA (Max) SMIA specification pliant CLASS 0 and CLASS 1,2 supported (config by CLASS_SEL) CMOS logic input threshold (EN, SYNC_SEL, CLASS_SEL): VIL = 0.3x VL; VL = 1.65V to 1.95V VIH = 0.7x VL; VL = 1.65V to 1.95V 3.6V tolerant on inputs (EN, SYNC_SEL, CLASS_SEL) 32 BIT synchronization codes (SOF, EOF, SOL, EOL) Leadfree µTFBGA package (Ro HS Restriction of hazardous substances) s µTFBGA25 s Description The STSMIA832 receiver converts the sub LVDS clock/datastream (up to 650 Mbps throughput bandwidth) back into parallel 8 bits of CMOS/LVTTL. The device recognizes the SMIA 32 bit start of frame (SOF), end of frame (EOF), start of line (SOL) and end of line (EOL) sequences to generate the H-SYNC and V-SYNC signals. Output LVTTL clock (up to 82 MHz) is transmitted in parallel with data. Output data are rising-edge strobes. This chipset is an ideal means to link mobile camera modules to Baseband processors. In order to minimize static current consumption, it is possible to shut down the device when the interface is not being used by a power-down (EN) pin that reduces the Maximum Current Consumption to 10 µA making this device ideal for portable applications like Mobile Phone and Portable Battery Equipment. A configurable input (Class_Sel) is provided to select different CLASS...