STPIC6A259 Datasheet | STMicroelectronics

.. POWER LOGIC 8-BIT ADDRESSABLE LATCH PRELIMINARY DATA s s s s s s s LOW RDS(on): 1Ω TYP OUTPUT SHORT-CIRCUIT PROTECTION 75m J AVAILANCHE ENERGY EIGHT 350m A DMOS OUTPUTS 50V SWITCHING CAPABILITY FOUR DISTINCT FUNCTION MODES LOW POWER CONSUMPTION DESCRIPTION This power logic 8-bit addressable latch controls open-drain DMOS transistor outputs and is designed for general-purpose storage applications in digital systems. Specific uses include working registers, serial-holding registers, and decoders or demultiplexers. This is a multifunctional device capable of operating as eight addressable latches or an 8-line demultiplexer with active-low DMOS outputs. Each open-drain DMOS transistor Features an independent chopping current-limiting circuit to prevent damage in the case of a short circuit. Four distinct modes of operation are selectable by controlling the clear (CLR) and enable (G) inputs and enumerated in the function table. In the addressable-latch mode, data at the data-in (D) terminal is written into the addressed latch. The addressed DMOS-transistor output inverts the data input with all unadressed DMOS-transistor output remaining in their previuous state. In the MOS-transistor outputs remain in their previous states and are unaffected by the data or address inputs. To eliminate the possibility of entering erroneus data in the latch, enable G should be ORDERING CODES Type STPIC6A259M STPIC6A259MTR held high (inactive) while the address lines are changing. In the 8-line demoultiplexing mode, the addressed output is inverted with respectto the D input and all other output are high. In the clear mode, all outputs are high and unaffected by the address and data inputs. Separate power ground (PGND) and logic ground (LGND) terminals are providied to facilitate maximum system flexibility. All PGND terminals are interally connected, and each p GND terminal must be externally connected to the power system ground in order to minimize...