STSLVDSP27 Datasheet | STMicroelectronics

.. 8-bit low voltage serializer with 1.8V high speed dual differential line drivers and embedded DPLL Features - - - Sub-low voltage differential signaling: VOD = 150m V with RT = 100Ω, CL = 10p F Clock range: 4 to 27 MHz in parallel mode, BYP = Gnd Operative frequency serial mode, BYP = VDD; DIN0 to DOUT, CLKIN to CLKOUT, f OPR = 1 to 208 MHz max Embedded DPLL requires no external ponents Output voltage rise and fall times tr VOD = tf VOD = 610ps typ at f OPR = 208MHz High speed propagation delay times tp LH~tp HL= 2.1ns typ at VDD = 3.0V; VIO = 1.8V Operating voltage range: VDD (OPR) = 2.5V to 3.6V VIO (OPR) = 1.65V to 1.95V High impedance on driver outputs IOZ = 1µA max; EN = Gnd; VO = Gnd or VIO Low voltage CMOS input threshold (DIN0-DIN7, CLKIN, EN, BYP, DVO, DV1) VIL = 0.3 x VDD max; VIH = 0.7 x VDD min 3.6V tolerant on all inputs (DIN0-DIN7, CLKIN, EN, BYP, DV0, DV1) Lead-free Flip-Chip package SMIA CCP1 (MIPI CSI-1) patible PHY Flip-Chip20 - - - - - - - - - Description The STSLVDSP27 is an 8:1 bit serializer with embedded DPLL. The dual differential line drivers implement the electrical characteristics of sub-low voltage differential signaling (sub LVDS), bringing out the serialized data and related synchronous clock signal. The STSLVDSP27 serializer IC is provided with two power supply rails, VDD and VIO. The first supply is related to the logic levels of the input data (DIN0-DIN7, CLKIN) and Enables (EN, BYP, DV0, DV1) pins. VIO provides the power supply to the output current drivers in the device. VIO is always expected to be a nominal 1.8V. VDD depends on the application, but will always be equal to or higher than VIO. In order to minimize static current consumption, it is possible to shut down the transmitters when the interface is not used by setting a power-down (EN) pin. This operation reduces the maximum current consumption to 20µA, making this device ideal for portable applications like mobile phones and portable...