K4H561638D-TCB3 Datasheet

Manufacturer: Samsung Semiconductor

This datasheet includes multiple variants, all published together in a single manufacturer document.

Datasheet Details

256Mb.

Double-data-rate architecture; two data transfers per clock cycle
Bidirectional data strobe(DQS)
Four banks operation
Differential clock inputs(CK and CK)
DLL aligns DQ and DQS transition with CK transition
MRS cycle with address key programs -. Read latency 2, 2.5 (clock) .. -. Burst length (2, 4, 8) -. Burst type (sequentia
All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
Data I/O transactions on both edges of data strobe
Edge aligned data output, center aligned data input
LDM,UDM/DM for write masking only

Part Number	Description
K4H561638F	256Mb F-die DDR SDRAM Specification
K4H561638F-TCC4	256Mb F-die DDR400 SDRAM Specification
K4H561638F-TCCC	256Mb F-die DDR400 SDRAM Specification
K4H561638F-UCC4	256Mb F-die DDR400 SDRAM
K4H561638F-UCCC	256Mb F-die DDR400 SDRAM
K4H561638H	(K4H560438H - K4H561638H) 256Mb H-die DDR SDRAM Specification
K4H561638J	256Mb J-die DDR SDRAM Specification
K4H560438D-TCB3	256Mb D-die DDR Sdram
K4H560438H	(K4H560438H - K4H561638H) 256Mb H-die DDR SDRAM Specification
K4H560438J	256Mb J-die DDR SDRAM Specification