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K7D161874B - 512Kx36 & 1Mx18 SRAM

Datasheet Summary

Description

The K7D163674B and K7D161874B are 18,874,368 bit Synchronous Pipeline Burst Mode SRAM devices.

They are organized as 524,288 words by 36 bits for K7D163674B and 1,048,576 words by 18 bits for K7D161874B, fabricated using Samsung's advanced CMOS technology.

Features

  • 512Kx36 or 1Mx18 Organizations. 1.8~2.5V VDD/1.5V VDDQ. (1.9V max VDDQ) HSTL Input and Outputs. Single Differential HSTL Clock. Synchronous Pipeline Mode of Operation with Self-Timed Late Write.
  • Free Running Active High and Active Low Echo Clock Output Pin.
  • Asynchronous Output Enable.
  • www. DataSheet4U. com 512Kx36 & 1Mx18 SRAM.
  • Registered Addresses, Burst Control and Data Inputs.
  • Registered Outputs.

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Datasheet Details

Part number K7D161874B
Manufacturer Samsung Semiconductor
File Size 470.08 KB
Description 512Kx36 & 1Mx18 SRAM
Datasheet download datasheet K7D161874B Datasheet
Additional preview pages of the K7D161874B datasheet.

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K7D163674B K7D161874B Document Title 16M DDR SYNCHRONOUS SRAM www.DataSheet4U.com 512Kx36 & 1Mx18 SRAM Revision History Rev No. Rev. 0.0 Rev. 0.1 History Initial document. Change JTAG DC OPERATING CONDITONS/AC TEST CONDITIONS -to support 1.8~2.5V VDD, change some items. Change DC CHARACTERISTICS (Stop Clock Standby Current) -ISB1 : 100 -> 150 Change JTAG Instruction Cording - For Reserved Change DC CHARACTERISTICS (Increase Operating Current) - x36 : add 40mA, x18 : add 60mA Add DC CHARACTERISTICS - VIN-CLK, VDIF-CLK, VCM-CLK Add AC INPUT CHARACTERISTICS Add INPUT DEFINITION Draft Data Oct. 2003 Nov. 2003 Remark Advance Preliminary Rev. 0.2 Feb. 2004 Preliminary Rev. 0.3 Feb. 2004 Preliminary Rev. 1.0 Mar. 2004 Final Rev. 1.1 Jan.
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