K7D163674B Description
The K7D163674B and K7D161874B are 18,874,368 bit Synchronous Pipeline Burst Mode SRAM devices. Single differential HSTL level clock, K and K are used to initiate the read/write operation and all internal operations are self-timed. At the rising edge of K clock, all addresses and burst control inputs are registered internally.
K7D163674B Key Features
- Free Running Active High and Active Low Echo Clock Output Pin
- Asynchronous Output Enable
- 512Kx36 & 1Mx18 SRAM
- Registered Addresses, Burst Control and Data Inputs
- Registered Outputs
- Double and Single Data Rate Burst Read and Write
- Burst Count Controllable With Max Burst Length of 4
- Interleved and Linear Burst mode support
- Bypass Operation Support
- Programmable Impedance Output Drivers