KM23C8105DET Datasheet | Samsung Semiconductor

FEATURES - Switchable organization 1,048,576 x 8(byte mode) 524,288 x 16(word mode) - Fast access time Random Access : 100ns(Max.) Page Access : 30ns(Max.) - 4 Words / 8 bytes page access - Supply voltage : single +5V - Current consumption Operating : 80m A(Max.) Standby : 50µA(Max.) - Fully static operation - All inputs and outputs TTL patible - Three state outputs - Package -. KM23C8105D(E)T : 44-TSOP2-400 CMOS MASK ROM GENERAL DESCRIPTION The KM23C8105D(E)T is a fully static mask programmable ROM fabricated using silicon gate CMOS process technology, and is organized either as 1,048,576 x 8 bit(byte mode) or as 524,288 x 16 bit(word mode) depending on BHE voltage level.(See mode selection table) This device includes page read mode function, page read mode allows 4 words (or 8bytes) of data to read fast in the same page, CE and A 2 ~ A18 should not be changed. This device operates with a 5V single power supply, and all inputs and outputs are TTL patible. Because of its asynchronous operation, it requires no external clock assuring extremely easy operation. It is suitable for use in program memory of microprocessor, and data memory, character generator. The KM23C8105D(E)T is packaged in a 44-TSOP2. FUNCTIONAL BLOCK DIAGRAM A18 X BUFFERS AND DECODER MEMORY CELL MATRIX (524,288x16/ 1,048,576x8) PRODUCT INFORMATION Product KM23C8105DT KM23C8105DET Operating Temp Range 0°C~70°C -20°C~85°C Vcc Range (Typical) 5.0V Speed (ns) 100 - . . . A2 PIN CONFIGURATION Y BUFFERS AND DECODER SENSE AMP. DATA OUT BUFFERS N.C A18 A17 A7 A6 A5 A4 A3 A2 1 2 3 4 5 6 7 8 9 44 N.C 43 N.C 42 A8 41 A9 40 A10 39 A11 38 A12 37 A13 36 A14 35 A15 34 A16 33 BHE 32 VSS 31 Q15 /A-1 30 Q7 29 Q14 28 Q6 27 Q13 26 Q5 25 Q12 24 Q4 23 VCC A0~A1 A-1 CE OE BHE Pin Name A 0 - A1 A2- A18 Q0 - Q14 Q15 /A-1 BHE CE OE VCC VSS N.C Pin Function Page Address Inputs Address Inputs Data Outputs Output 15(Word mode)/ LSB Address(Byte mode) Word/Byte selection Chip Enable Output Enable Power ( +5V) Ground...