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K4S560832C
CMOS SDRAM
256Mbit SDRAM
8M x 8bit x 4 Banks Synchronous DRAM LVTTL
Revision 0.1 Sept. 2001
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 0.1 Sept. 2001
K4S560832C
Revision History Revision 0.0 (Mar. 06, 2001) Revision 0.1 (Sep. 06, 2001)
• •
CMOS SDRAM
Redefined IDD1 & IDD4 in DC Characteristics Changed the Notes in Operating AC Parameter. < Before > 5. For 1H/1L, tRDL=1CLK and tDAL=1CLK+tRP is also supported . SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP. < After > 5.In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
Rev. 0.1 Sept. 2001
K4S560832C
8M x 8Bit x 4 Banks Synchronous DRAM
FEATURES
• JEDEC standard 3.