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K4S560832D - 256Mbit SDRAM 8M x 8bit x 4 Banks Synchronous DRAM LVTTL

Description

The K4S560832D is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 8,392,608 words by 8bits, fabricated with SAMSUNG's high performance CMOS technology.

Features

  • JEDEC standard 3.3V power supply.
  • LVTTL compatible with multiplexed address.
  • Four banks operation.
  • MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave).
  • All inputs are sampled at the positive going edge of the system clock.
  • Burst read single-bit write operation.
  • DQM for masking.
  • Auto & self refresh.
  • 64ms refresh period (8K Cycle.

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Other Datasheets by Samsung Semiconductor

Part Number Description
K4S560832A 256Mbit SDRAM 8M x 8bit x 4 Banks Synchronous DRAM LVTTL
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K4S560832C 256Mbit SDRAM 8M x 8bit x 4 Banks Synchronous DRAM LVTTL
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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K4S560832D CMOS SDRAM 256Mbit SDRAM 8M x 8bit x 4 Banks Synchronous DRAM LVTTL Revision 1.1 May. 2003 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 1.1 May. 2003 K4S560832D Revision History Revision 0.0 (Jan. , 2002) - First release CMOS SDRAM Revision 0.1(May., 2003) - ICC6 of Low power is changed from 1.0 to 1.5 due to typo. Rev. 1.1 May. 2003 K4S560832D 8M x 8Bit x 4 Banks Synchronous DRAM FEATURES • JEDEC standard 3.3V power supply • LVTTL compatible with multiplexed address • Four banks operation • MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock.
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