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K4S643232C - 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL

Download the K4S643232C datasheet PDF. This datasheet also covers the K4S variant, as both devices belong to the same 2m x 32 sdram 512k x 32bit x 4 banks synchronous dram lvttl family and are provided as variant models within a single manufacturer datasheet.

General Description

The K4S643232C is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits, fabricated with SAMSUNG′s high performance CMOS technology.

Synchronous design allows precise cycle control with the use of system clock.

Key Features

  • 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst read single-bit write operation DQM for masking Auto & self refresh 15.6us refresh duty cycle CMOS SDRAM.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (K4S-6432.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
K4S643232C CMOS SDRAM 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL Revision 1.1 November 1999 Samsung Electronics reserves the right to change products or specification without notice. -1- REV. 1.1 Nov. '99 K4S643232C Revision History Revision 1.1 (November 17th, 1999) • Corrected typo in ordering information on page 3 CMOS SDRAM Revision 1.0 (October, 1999) • Changed part number from KM432S2030CT-G/F to K4S643232C-TC/TL according to re-organized code system -2- REV. 1.1 Nov. '99 K4S643232C 512K x 32Bit x 4 Banks Synchronous DRAM FEATURES • • • • 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -.