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K4X51323PC-8E - 16M x32 Mobile-DDR SDRAM

Download the K4X51323PC-8E datasheet PDF. This datasheet also covers the K4X51323PC-7E variant, as both devices belong to the same 16m x32 mobile-ddr sdram family and are provided as variant models within a single manufacturer datasheet.

General Description

Clock : CK and CK are differential clock inputs.

All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK.

Internal clock signals are derived from CK/CK.

Key Features

  • Mobile-DDR SDRAM.
  • 1.8V power supply, 1.8V I/O power.
  • Double-data-rate architecture; two data transfers per clock cycle.
  • Bidirectional data strobe(DQS).
  • Four banks operation.
  • 1 /CS.
  • 1 CKE.
  • Differential clock inputs(CK and CK).
  • MRS cycle with address key programs - CAS Latency ( 2, 3 ) - Burst Length ( 2, 4, 8, 16 ) - Burst Type (Sequential & Interleave) - Partial Self Refresh Type ( Full, 1/2, 1/4 Array ) - Output Driver St.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (K4X51323PC-7E_Samsungsemiconductor.pdf) that lists specifications for multiple related part numbers.

Other Datasheets by Samsung Semiconductor

Part Number Description
K4X51323PC-8G 16M x32 Mobile-DDR SDRAM
K4X51323PC-7E 16M x32 Mobile-DDR SDRAM
K4X51323PC-7G 16M x32 Mobile-DDR SDRAM
K4X51163PC 32M x16 Mobile-DDR SDRAM
K4X51163PC-FE 32M x16 Mobile-DDR SDRAM
K4X51163PC-FG 32M x16 Mobile-DDR SDRAM
K4X51163PC-LE 32M x16 Mobile-DDR SDRAM
K4X51163PC-LG 32M x16 Mobile-DDR SDRAM
K4X51163PE-FG 32Mx16 Mobile DDR SDRAM
K4X51163PE-LE 32Mx16 Mobile DDR SDRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
Preliminary K4X51323PC - 7(8)E/G Mobile-DDR SDRAM www.DataSheet4U.com 16M x32 Mobile-DDR SDRAM 1 Revision 0.6 October 2005 Preliminary K4X51323PC - 7(8)E/G Document Title 16M x32 Mobile-DDR SDRAM Mobile-DDR SDRAM Revision History Revision No. History 0.0 0.1 0.2 - First version for target specification - Insertion of PKG dimension of 90FBGA JEDEC Standard type. - Preliminary Datasheet - Insertion DC Current value. - Changing Frequency from DDR333/DDR266 to DDR266/DDR222. - Updating DC current value. - Changing expression of PKG dimension. - Changing format with JEDEC standard type. - Insertion of Normal power bin. - Changing IDD3P/3PS - Changing IDD6 limit. - Define maximum burst refresh cycle. - Add a note related with Vdd & Vddq. - Add a note related with IDD8.