K4Y50044UC - (K4Y50024UC - K4Y50164UC) 512Mbit XDR TM DRAM

This page provides the datasheet information for the K4Y50044UC, a member of the K4Y50024UC (K4Y50024UC - K4Y50164UC) 512Mbit XDR TM DRAM family.

Description

The timing diagrams in Figure 1 illustrate XDR DRAM device write and read transactions.

There are three sets of pins used for normal memory access transactions: CFM/CFMN clock pins, RQ11..0 request pins, and DQ15..0/DQN15..0 data pins.

Features

Highest pin bandwidth available - 4000/3200/2400 Mb/s Octal Data Rate(ODR) Signaling.
Bi-directional differential RSL(DRSL) - Flexible read/write bandwidth allocation - Minimum pin count.
On-chip termination - Adaptive impedance matching - Reduced system cost and routing complexity.
Highest sustained bandwidth per DRAM device - Up to 8000 MB/s sustained data rate - Eight banks : bank-interleaved transaction at full bandwidth - Dynamic request scheduling - Ear.

Samsung semiconductor

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Datasheet Details

Part number	K4Y50044UC
Manufacturer	Samsung semiconductor
File Size	3.39 MB
Description	(K4Y50024UC - K4Y50164UC) 512Mbit XDR TM DRAM
Datasheet	K4Y50044UC Datasheet
Additional preview pages of the K4Y50044UC datasheet.

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www.DataSheet4U.com K4Y50164UC K4Y50084UC K4Y50044UC K4Y50024UC XDRTM DRAM 512Mbit XDR TM DRAM(C-die) Revision 1.1 August 2006 INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2.

Published: Mar 22, 2007 |