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K4Y54084UF - XDR/RDRAM

Description

The timing diagrams in Figure 1 illustrate XDR DRAM device write and read transactions.

There are three sets of pins used for normal memory access transactions: CFM/CFMN clock pins, RQ11..0 request pins, and DQ15..0/DQN15..0 data pins.

Features

  • Highest pin bandwidth available - 4000/3200/2400 Mb/s Octal Data Rate(ODR) Signaling.
  • Bi-directional differential RSL(DRSL) - Flexible read/write bandwidth allocation - Minimum pin count.
  • Programmable on-chip termination - Adaptive impedance matching - Reduced system cost and routing complexity.
  • Highest sustained bandwidth per DRAM device - Up to 8000 MB/s sustained data rate - Eight banks : bank-interleaved transaction at full bandwidth - Dynamic request sch.

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Datasheet Details

Part number K4Y54084UF
Manufacturer Samsung Semiconductor
File Size 3.45 MB
Description XDR/RDRAM
Datasheet download datasheet K4Y54084UF Datasheet
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www.DataSheet4U.com K4Y5416(/08/04)4UF XDR DRAM 256Mbit XDR DRAM(F-die) 2M x 16(/8/4) bit x 8s Banks Version 1.0 Jan. 2005 Version 1.0 Jan. 2005 Page -1 www.DataSheet4U.com K4Y5416(/08/04)4UF Change History Version 0.1( July 2004) - Preliminary - First Copy - Based on the Rambus XDR DRAMTM Datasheet Version 0.81 XDR DRAM Version 1.0( Jan. 2005) - Delete “Preliminary” - Based on the Rambus XDR DRAMTM Datasheet Version 0.85 Version 1.0 Jan. 2005 Page 0 www.DataSheet4U.com K4Y5416(/08/04)4UF Overview XDR DRAM The Rambus XDR DRAM device is a general-purpose high-performance memory device suitable for use in a broad range of applications, including computer memory, graphics, video, and any other application where high bandwidth and low latency are required.
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