Datasheet Details
| Part number | K4Y50084UC |
|---|---|
| Manufacturer | Samsung Semiconductor |
| File Size | 3.39 MB |
| Description | (K4Y50024UC - K4Y50164UC) 512Mbit XDR TM DRAM |
| Datasheet |
 K4Y50084UC Datasheet
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General Description
The timing diagrams in Figure 1 illustrate XDR DRAM device write and read transactions.
There are three sets of pins used for normal memory access transactions: CFM/CFMN clock pins, RQ11..0 request pins, and DQ15..0/DQN15..0 data pins.
Key Features
- Highest pin bandwidth available - 4000/3200/2400 Mb/s Octal Data Rate(ODR) Signaling.
- Bi-directional differential RSL(DRSL) - Flexible read/write bandwidth allocation - Minimum pin count.
- On-chip termination - Adaptive impedance matching - Reduced system cost and routing complexity.
- Highest sustained bandwidth per DRAM device - Up to 8000 MB/s sustained data rate - Eight banks : bank-interleaved transaction at full bandwidth - Dynamic request scheduling - Ear.