K7B163625A Datasheet | Samsung Semiconductor

FEATURES - Synchronous Operation. - On-Chip Address Counter. - Self-Timed Write Cycle. - On-Chip Address and Control Registers. - 3.3V+0.165V/-0.165V Power Supply. - I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O - 5V Tolerant Inputs Except I/O Pins. - Byte Writable Function. - Global Write Enable Controls a full bus-width write. - Power Down State via ZZ Signal. - LBO Pin allows a choice of either a interleaved burst or a linear burst. - Three Chip Enables for simple depth expansion with No Data Contention only for TQFP. - Asynchronous Output Enable Control. - ADSP , ADSC, ADV Burst Control Pins. - TTL-Level Three-State Output. - 100-TQFP-1420A - Operating in meical and industrial temperature range. GENERAL DESCRIPTION The K7B163625A and K7B161825A are 18,874,368-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System. It is organized as 512K(1M) words of 36(32/18) bits and integrates address and control registers, a 2-bit burst address counter and added some new functions for high performance cache RAM applications; GW, BW, LBO, ZZ. Write cycles are internally self-timed and synchronous. Full bus-width write is done by GW, and each byte write is performed by the bination of W Ex and BW when G W is high. And with CS 1 high, ADSP is blocked to control signals. Burst cycle can be initiated with either the address status processor(ADSP) or address status cache controller(ADSC) inputs. Subsequent burst addresses are generated internally in the system′ s burst sequence and are controlled by the burst address advance(ADV) input. LBO pin is DC...