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K7B321825M - 1Mx36 & 2Mx18 Synchronous SRAM

General Description

The K7B323625M and K7B321825M are 37,748,736-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System.

Key Features

  • Synchronous Operation.
  • On-Chip Address Counter.
  • Self-Timed Write Cycle.
  • On-Chip Address and Control Registers.
  • 3.3V+0.165V/-0.165V Power Supply.
  • I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O.
  • 5V Tolerant Inputs Except I/O Pins.
  • Byte Writable Function.
  • Global Write Enable Controls a full bus-width write.
  • Power Down State via ZZ Signal.
  • LBO Pin allows.

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Full PDF Text Transcription for K7B321825M (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for K7B321825M. For precise diagrams, and layout, please refer to the original PDF.

K7B323625M K7B321825M Document Title 1Mx36 & 2Mx18 Synchronous SRAM 1Mx36 & 2Mx18-Bit Synchronous Burst SRAM Revision History Rev. No. 0.0 0.1 0.2 0.3 History 1. Initial ...

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rst SRAM Revision History Rev. No. 0.0 0.1 0.2 0.3 History 1. Initial draft 1. Add 165FBGA package 1. Update JTAG scan order 1. Change pin out for 165FBGA - x18/x36 ; 11B => from A to NC , 2R ==> from NC to A . 1. Insert pin at JTAG scan order of 165FBGA in connection with pin out change - x18/x36 ; insert Pin ID of 2R to BIT number of 69 1. Add Icc, Isb, Isb1 and Isb2 values. 1. Correct the pin name of 100TQFP. 1. Change the Stand-by current (Isb) Before After Isb - 65 : 100 140 - 75 : 90 130 - 85 : 80 130 Isb1 : 90 110 Isb2 : 80 100 1. Delete the 119BGA and 165FBGA package. 2. Delete the 8.5ns speed bin Draft Date May. 1

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