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K7P321866M - 1Mx36 & 2Mx18 SRAM

General Description

Pin Name K, K SAn DQn SW SWa SWb SWc SWd ZZ VDD VDDQ Pin Description Differential Clocks Synchronous Address Input Bi-directional Data Bus Synchronous Global Write Enable Synchronous Byte a Write Enable Synchronous Byte b Write Enable Synchronous Byte c Write Enable Synchronous Byte d Write Enable A

Key Features

  • 1Mx36 or 2Mx18 Organizations.
  • 2.5V Core/1.5V Output Power Supply (1.9V max VDDQ).
  • HSTL Input and Output Levels.
  • Differential, HSTL Clock Inputs K, K.
  • Synchronous Read and Write Operation.
  • Registered Input and Registered Output.
  • Internal Pipeline Latches to Support Late Write.
  • Byte Write Capability(four byte write selects, one for each 9bits).
  • Synchronous or Asynchronous Output Enable.
  • Power Down Mode.

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Full PDF Text Transcription for K7P321866M (Reference)

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K7P323666M K7P321866M www.DataSheet4U.com 1Mx36 & 2Mx18 SRAM 32Mb M-die LW SRAM Specification 119BGA with Pb & Pb-Free (RoHS compliant) INFORMATION IN THIS DOCUMENT IS PR...

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with Pb & Pb-Free (RoHS compliant) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2.