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KM432S2030C - 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL

Datasheet Summary

Description

The KM432S2030C is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits, fabricated with SAMSUNG′s high performance CMOS technology.

Synchronous design allows precise cycle control with the use of system clock.

Features

  • 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst read single-bit write operation DQM for masking Auto & self refresh 15.6us refresh duty cycle CMOS SDRAM.

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Datasheet Details

Part number KM432S2030C
Manufacturer Samsung semiconductor
File Size 1.13 MB
Description 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL
Datasheet download datasheet KM432S2030C Datasheet
Additional preview pages of the KM432S2030C datasheet.

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Full PDF Text Transcription

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KM432S2030C CMOS SDRAM 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL Revision 1.1 March 1999 Samsung Electronics reserves the right to change products or specification without notice. -1- REV. 1.1 Mar. '99 KM432S2030C Revision History CMOS SDRAM Revision 1.1 (March 12th, 1999) • Corrected typo in ordering information on page 3 Revision 1.0 (March 8th, 1999) - Final Spec • Removed KM432S2030C-Z@CL2 part (125MHz@CL2) • Changed tRDL from 1CLK to 2CLK for every clock frequency. For -6/7/8/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV" Revision 0.3 (March 5th, 1999) - Preliminary Spec Revision 0.
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