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KM48S8030C Datasheet 2M x 8Bit x 4 Banks Synchronous DRAM

Manufacturer: Samsung Semiconductor

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General Description

The KM48S8030C is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 8 bits, fabricated with SAMSUNG′s high performance CMOS technology.

Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.

Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

Overview

KM48S8030C Revision History Revision 0.0 (Oct., 1998) • PC133 first published.

Preliminary PC133 CMOS SDRAM REV.

0 Oct.

Key Features

  • JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency 3 only -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst read single-bit write operation DQM for masking Auto & self refresh 64ms refresh period (4K Cycle) Preliminary PC133 CMOS SDRAM.

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