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KM681001A - 128K x 8 Bit High-Speed CMOS Static RAM

Datasheet Summary

Description

The KM681001A is a 1,048,576-bit high-speed Static Random Access Memory organized as 131,072 words by 8 bits.

The KM681001A uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle.

Features

  • Fast Access Time 15, 20ns(Max. ).
  • Low Power Dissipation Standby (TTL) : 25mA(Max. ) (CMOS) : 8mA(Max. ) Operating KM681001A - 15 : 125mA(Max. ) KM681001A - 20 : 120mA(Max. ).
  • Single 5.0V ±10% Power Supply.
  • TTL Compatible Inputs and Outputs.
  • I/O Compatible with 3.3V Device.
  • Fully Static Operation -No Clock or Refresh required.
  • Three State Outputs www. DataSheet4U. com.
  • Standard Pin Configuration KM681001AJ : 32-SOJ-400 CMOS SRAM G.

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Datasheet Details

Part number KM681001A
Manufacturer Samsung semiconductor
File Size 149.83 KB
Description 128K x 8 Bit High-Speed CMOS Static RAM
Datasheet download datasheet KM681001A Datasheet
Additional preview pages of the KM681001A datasheet.

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Full PDF Text Transcription

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PRELIMINARY KM681001A Document Title 128Kx8 High Speed Static RAM(5V Operating), Evolutionary Pin Out. Operated at Commercial Temperature Range. CMOS SRAM Revision History Rev. No. Rev. 0.0 Rev. 1.0 History Initial release with Design Target. Release to Preliminary Data Sheet. 1.1. Replace Design Target to Preliminary Release to final Data Sheet. 2.1. Delete Preliminary Update D.C and A.C parameters. 3.1. Update D.C parameters Previous spec. Items (15/17/20ns part) Icc 190/180/170mA Isb 30mA Isb1 10mA 3.2. Update A.C parameters Previous spec. Items (15/17/20ns part) tCW 12/12/13ns tAW 12/12/13ns tWP1(OE=H) 12/12/13ns tDW 8/9/10ns Draft Data Jan. 18th, 1995 Apr. 22th, 1995 Remark Design Target Preliminary www.DataSheet4U.com Rev. 2.0 Feb. 29th, 1996 Final Rev. 3.0 Jul.
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