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KM681001B - 128K x 8 Bit High-Speed CMOS Static RAM

Datasheet Summary

Description

The KM681001B is a 1,048,576-bit high-speed Static Random Access Memory organized as 131,072 words by 8 bits.

The KM681001B uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle.

Features

  • Fast Access Time 15, 20ns(Max. ).
  • Low Power Dissipation Standby (TTL) : 20mA(Max. ) (CMOS) : 5mA(Max. ) Operating KM681001B - 15 : 125mA(Max. ) KM681001B - 20 : 123mA(Max. ).
  • Single 5.0V±10% Power Supply.
  • TTL Compatible Inputs and Outputs.
  • Fully Static Operation - No Clock or Refresh required.
  • Three State Outputs www. DataSheet4U. com.
  • Standard Pin Configuration KM681001BJ : 32-SOJ-400 KM681001BSJ : 32-SOJ-300 CMOS SRAM.

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Datasheet Details

Part number KM681001B
Manufacturer Samsung semiconductor
File Size 159.67 KB
Description 128K x 8 Bit High-Speed CMOS Static RAM
Datasheet download datasheet KM681001B Datasheet
Additional preview pages of the KM681001B datasheet.

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Full PDF Text Transcription

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PRELIMINARY KM681001B Document Title 128Kx8 Bit High Speed Static RAM(5V Operating), Evolutionary Pin out. Operated at Commercial and Industrial Temperature Range. CMOS SRAM Revision History Rev . No. Rev. 0.0 Rev. 1.0 History Initial release with Design Target. Release to Preliminary Data Sheet. 1. Replace Design Target to Preliminary. Release to Final Data Sheet. 1. Delete Preliminary. 2. Delete 17ns, L-version and Industrial Temperature Part. 3. Delete Voh1=3.95V. 4. Delete Data Retention Characteristics and Wave form. 5. Relex operating current Speed Previous Now 15ns 130mA 125mA 17ns 120mA 20ns 110mA 123mA Draft Data Feb. 1st, 1997 Jun. 1st, 1997 Remark Design Target Preliminary www.DataSheet4U.comRev. 2.0 Feb. 6th.
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