KM681001B Datasheet | Samsung Semiconductor

PRELIMINARY Document Title 128Kx8 Bit High Speed Static RAM(5V Operating), Evolutionary Pin out. Operated at mercial and Industrial Temperature Range. CMOS SRAM Revision History Rev . No. Rev. 0.0 Rev. 1.0 History Initial release with Design Target. Release to Preliminary Data Sheet. 1. Replace Design Target to Preliminary. Release to Final Data Sheet. 1. Delete Preliminary. 2. Delete 17ns, L-version and Industrial Temperature Part. 3. Delete Voh1=3.95V. 4. Delete Data Retention Characteristics and Wave form. 5. Relex operating current Speed Previous Now 15ns 130m A 125m A 17ns 120m A 20ns 110m A 123m A Draft Data Feb. 1st, 1997 Jun. 1st, 1997 Remark Design Target Preliminary ..Rev. 2.0 Feb. 6th. 1998 Final The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. Rev 2.0 February 1998 -1- PRELIMINARY 128K x 8 Bit High-Speed CMOS Static RAM Features - Fast Access Time 15, 20ns(Max.) - Low Power Dissipation Standby (TTL) : 20m A(Max.) (CMOS) : 5m A(Max.) Operating KM681001B - 15 : 125m A(Max.) KM681001B - 20 : 123m A(Max.) - Single 5.0V±10% Power Supply - TTL patible Inputs and Outputs - Fully Static Operation - No Clock or Refresh required - Three State Outputs .. - Standard Pin Configuration KM681001BJ : 32-SOJ-400 KM681001BSJ : 32-SOJ-300 CMOS SRAM GENERAL DESCRIPTION The KM681001B is a 1,048,576-bit high-speed Static Random Access Memory organized as 131,072 words by 8 bits. The KM681001B uses 8 mon input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using Samsung′s advanced CMOS process and designed...