KM736FV4021 - (KM736FV4021 / KM718FV4021) 128Kx36 & 256Kx18 Synchronous Pipelined SRAM

Datasheet Summary

Description

Pin Name K, K SAn DQn SW SWa SWb SWc SWd ZZ VDD Pin Description Differential Clocks Synchronous Address Input Bi-directional Data Bus Synchronous Global Write Enable Synchronous Byte a Write Enable Synchronous Byte b Write Enable Synchronous Byte c Write Enable Synchronous Byte d Write Enable Asynch

Features

128Kx36 or 256Kx18 Organizations. 3.3V Core Power Supply. LVTTL Input and Output Levels. Differential, PECL Clock Inputs K, K. Synchronous Read and Write Operation Registered Input and Registered Output Internal Pipeline Latches to Support Late Write. Byte Write Capability(four byte write selects, one for each 9bits) Synchronous or Asynchronous Output Enable. Power Down Mode vi.

Samsung semiconductor

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Datasheet Details

Part number	KM736FV4021
Manufacturer	Samsung semiconductor
File Size	350.04 KB
Description	(KM736FV4021 / KM718FV4021) 128Kx36 & 256Kx18 Synchronous Pipelined SRAM
Datasheet	KM736FV4021 Datasheet
Additional preview pages of the KM736FV4021 datasheet.

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Full PDF Text Transcription

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KM736FV4021 KM718FV4021 Document Title 128Kx36 & 256Kx18 Synchronous Pipelined SRAM 128Kx36 & 256Kx18 SRAM Revision History Rev. No. Rev. 0.0 Rev. 0.1 History - Preliminary specification release - Change specification format. No change was made in parameters. - Updated IDD, ISB and Input High Level. Updated tKHKL, tKLKH, tKHQX, tKHQX1 and AC Test Conditions. For JTAG, updated Vendor Definition and added tSVCH/tCHSX. - Final specification release Draft Date Remark Preliminary April, 1997 Preliminary Rev. 0.2 Jan. 1998 Preliminary Rev. 1.0 Dec. 1998 Final The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications.

Published: Oct 28, 2005 |