K4E160812D Datasheet | Samsung Semiconductor

DESCRIPTION This is a family of 2,097,152 x 8 bit Extended Data Out CMOS DRAMs. Extended Data Out Mode offers high speed random access of memory cells within the same row, so called Hyper Page Mode. Power supply voltage (+5.0V or +3.3V), refresh cycle (2K Ref. or 4K Ref.), access time (-50 or -60), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 2Mx8 EDO Mode DRAM family is fabricated using Samsung′s advanced CMOS process to realize high band-width, low power consumption and high reliability. It may be used as graphic memory unit for microputer and personal puter. FEATURES - Part Identification - K4E170811D-B(F) (5V, 4K Ref.) - K4E160811D-B(F) (5V, 2K Ref.) - K4E170812D-B(F) (3.3V, 4K Ref.) - K4E160812D-B(F) (3.3V, 2K Ref.) - Active Power Dissipation Unit : m W Speed 4K -50 -60 324 288 3.3V 2K 396 360 4K 495 440 5V 2K 605 550 - Extended Data Out Mode operation (Fast page mode with Extended Data Out) - CAS-before-RAS refresh capability - RAS-only and Hidden refresh capability - Self-refresh capability (L-ver only) - Fast parallel test mode capability - TTL(5V)/LVTTL(3.3V) patible inputs and outputs - Early Write or output enable controlled write - JEDEC Standard pinout - Available in Plastic SOJ and TSOP(II) packages - Single +5V±10% power supply (5V product) - Single +3.3V±0.3V power supply (3.3V product) - Refresh Cycles Part NO. K4E170811D K4E170812D K4E160811D K4E160812D VCC 5V 3.3V 5V 3.3V 2K 32ms Refresh cycle 4K Refresh period Normal 64ms 128ms L-ver RAS CAS W FUNCTIONAL BLOCK DIAGRAM Control Clocks Vcc Vss VBB Generator Data in Refresh Timer Refresh Control Refresh Counter Memory Array 2,097,152 x8 Cells Row Decoder Sense Amps & I/O Buffer DQ0 to DQ7 - Performance Range Speed -50 -60 t RAC 50ns 60ns t CAC 13ns 15ns t RC 84ns...