K7P401822M Datasheet | Samsung Semiconductor

FEATURES - 128Kx36 or 256Kx18 Organizations. - 3.3V Core Power Supply. - LVTTL Input and Output Levels. - Differential, PECL Clock Inputs K, K. - Synchronous Read and Write Operation - Registered Input and Registered Output - Internal Pipeline Latches to Support Late Write. - Byte Write Capability(four byte write selects, one for each 9bits) - Synchronous or Asynchronous Output Enable. - Power Down Mode via ZZ Signal. - JTAG 1149.1 patible Test Access port. - 119(7x17)Pin Ball Grid Array Package(14mmx22mm) Organization Part Number 128Kx36 256Kx18 K7P403622M-H20 K7P403622M-H16 K7P403622M-H19 K7P401822M-H20 K7P401822M-H16 K7P401822M-H19 Cycle Time 5 6 7 5 6 7 Access Time 2.5 3.0 3.5 2.5 3.0 3.5 FUNCTIONAL BLOCK DIAGRAM SA[0:16] or SA[0:17] CK SS SW SWx (x=a, b, c, d) or (x=a, b) Latch Latch SW Register SWx Register SS Register Read Address Register SW Register SWx Register SS Register Write Address Register G...