Description
Pin Name K, K SAn DQn SS SW SWa SWb SWc SWd
M1, M2
Pin Description Differential Clocks Synchronous Address Input Bi-directional Data Bus Synchronous Select Synchronous Global Write Enable Synchronous Byte a Write Enable Synchronous Byte b Write Enable Synchronous Byte c Write Enable Synchronous By
Features
- 128Kx36 or 256Kx18 Organizations.
- 3.3V VDD, 2.5/3.3V VDDQ.
- LVTTL Input and Output Levels.
- Differential, PECL clock / Single ended or differential LVTTL
clock Inputs.
- Synchronous Read and Write Operation.
- Registered Input and Registered Output.
- Internal Pipeline Latches to Support Late Write.
- Byte Write Capability(four byte write selects, one for each 9bits).
- Synchronous or Asynchronous Output Enable.
K7P403622B Datasheet
