SK10E131 Datasheet | SEMTECH

SK10/100E131 HIGH-PER.ORMANCE PRODUCTS Description The SK10E/100E131 is a Quad master-slave D-type flipflop with differential outputs. Each flip-flop may be clocked separately by holding mon Clock (CC) LOW and using the Clock Enable (CE- ) inputs for clocking. mon clocking is achieved by holding the CE inputs LOW and using CC to clock all four flip-flops. In this case, the CE- inputs perform the function of controlling the mon clock to each flip-flop. 4-Bit D .lip-.lop Features - - - - - - - - 1100 MHz Minimum Toggle Frequency Differential Outputs Individual and mon Clocks Individual Resets (asynchronous) Paired Sets (asynchronous) Extended 100E VEE Range of - 4.2V to - 5.5V 75KΩ Internal Input Pulldown Resistors Fully patible with MC10E131 and MC100E131 Specified Over Industrial Temperature Range: - 40o C to 85o C ESD Protection of >4000V Available in 28-pin PLCC Package Individual asynchronous resets are provided (R). - Asynchronous set controls (S) are ganged together in pairs, with the pairing chosen to reflect physical chip - symmetry. - Data enters the master when both CC and CE- are LOW, and transfers to the slave when either CC or CE (or both) go HIGH. PIN Description Pin Names Functional Block Diagram Pin D0 - D3 CE0- - CE3- R0 - R3 CC S03, S12 Q0 - Q3 Q0- - Q3- .unction Data Inputs Clock Enables (individual) Resets mon Clock Sets (paired) True Outputs Inver ting Outputs D3 CE3- Q3 Q3- R R3 D2 CE2-...