SK10E151 Datasheet | SEMTECH

SK10/100E151 6-Bit D Register HIGH-PER.ORMANCE PRODUCTS Description The SK10/100E151 offers 6 edge-triggered, high-speed, master-slave D-type flip-flops with differential outputs, designed for use in new high-performance ECL systems. This device is fully patible with MC10E151 and MC100E151. The two external clock signals (CLK1, CLK2) are gated through a logical OR operation before use as clocking control for the flip-flops. Data is clocked into the flip-flops on the rising edge of either CLK1 or CLK2 (or both). When both CLK1 and CLK2 are at a logic LOW, data enters the master and is transferred to the slave when either CLK or CLK2 (or both) go HIGH. The MR (Master Reset) signal operates asynchronously to make all Q outputs go to a logic LOW. .eatures - - - - - - - - - - 1100 MHz Toggle Frequency Extended 100E VEE Range of - 4.2V to - 5.46V Differential Outputs Asynchronous Master Reset Dual Clocks Internal 75KΩ Input Pull-Down Resistors ESD Protection of >4000V Fully patible with MC10E/100E151 Specified Over Industrial Temperature Range: - 40o C to +85o C Available in 28-Pin PLCC Package PIN Description .unctional Block Diagram Pin D0–D5 CLK1, CLK2 D0 D R Q0 Q0- .unction Data Inputs Clock Inputs Master Reset True Outputs Inver ting Outputs VCC to Output MR Q0–Q5 D1 Q1 Q1- Q0- –Q5- VCC0 D2 Q2 Q2- VCC0 CLK2 CLK1 D3 Q3 Q5- 20 Q3-...