SK10E142 Datasheet | SEMTECH

SK10/100E142 9-Bit Shift Register HIGH-PER.ORMANCE PRODUCTS Description The SK10E/100E142 is a 9-bit shift register, designed with byte-parity applications in mind. The E142 performs serial/parallel in and serial/parallel out, shifting in one direction. The nine inputs D0 - D8 accept parallel input data, while S-IN accepts serial input data. The Qn outputs do not need to be terminated for the shift operation to function. To minimize noise and power, any Q output not used should be left unterminated. The SEL (Select) input pin is used to switch between the two modes of operation - SHIFT and LOAD. The shift direction is from bit 0 to bit 8. Input data is accepted by the registers at set-up time before the posiitive going edge of CLK1 or CLK2. Shifting is also acplished on the positive clock edge. A HIGH on the Master Reset pin (MR) asynchronously resets all the registers to zero. .eatures - - - - - - - - - - 700 MHz Minimum Shift Frequency 9-Bit for Byte-Parity Applications Asynchronous Master Reset Dual Clocks Extended 100E VEE Range of - 4.2 to - 5.5V 75KΩ Internal Input Pulldown Resistors Fully patible with MC10E142 and MC100E142 Specified over Industrial Temperature Range: - 40o C to 85o C ESD Protection of >4000V Available in 28-pin PLCC Package PIN Description Pin Names Pin .unction Parallel Data Inputs Serial Data Input Mode Select Input Clock Inputs Master Reset Data Outputs .unctional Block Diagram S-IN 1 D0 0 D Q Q0 D0 - D8 S-IN SEL CLK1, CLK2 MR Q0 - Q8 1 D1 0 Q1 Pinout VCC0 1 D2 0 Q2 25 MR CLK1 CLK2 VEE S-IN D0 D1 26 27...