SI53108 Datasheet | Silicon Labs

Features - Eight 0.7 V low-power, push-pull, - 1.05 to 3.3 V power supply HCSL-patible PCIe Gen 3 voltage outputs - Low phase jitter (Intel QPI, PCIe - Individual OE HW pins for each Gen 1/2/3/4 mon clock output clock pliant - 100 MHz /133 MHz PLL operation, supports PCIe and QPI - SMBus address is 0x D8 - PLL or bypass mode - Spread spectrum tolerable - Gen 3 SRNS pliant - Industrial Temperature: - 40 to 85 °C - 48-pin QFN - For higher output devices or variations of this device, contact Silicon Labs Applications - Server - Storage - Datacenter - Enterprise Switches and Routers Ordering Information: See page 32. Patents pending Description The Si53108 is a low-power, 8-output, differential clock buffer that meets all of the performance requirements of the Intel DB800ZL specification. The device is optimized for distributing reference clocks for Intel® Quick Path Interconnect (Intel QPI), PCIe Gen 1/Gen 2/Gen 3/Gen 4, SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI) applications. The VCO of the device is optimized to support 100 MHz and 133 MHz operation. Each differential output has a dedicated hardware output enable pin for maximum flexibility and power savings. Measuring PCIe clock jitter is quick and easy with the Silicon Labs PCIe Clock Jitter Tool. Download it for free at .silabs./pcie-learningcenter. Rev. 1.2 12/15 Copyright © 2015 by Silicon Laboratories Functional Block Diagram OE_[7:0] 8 CLK_IN CLK_IN SSC patible PLL 100M_133 HBW_BYPASS_LBW PWRGD / PWRDN SDA SCL Control Logic FB_OUT DIF_[7:0] 2 Rev. 1.2 TABLE OF CONTENTS Section Page 1. Electrical Specifications -...