SI5326 Description
The Si5326 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance. The Si5326 accepts two input clocks ranging from 2 kHz to 710 MHz and generates two output clocks ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The two outputs are divided down separately from a mon source.
SI5326 Key Features
- Generates any frequency from 2 kHz
- Dual clock outputs with selectable
- Support for ITU G.709 and custom
- Ultra-low jitter clock outputs with jitter 255/236)
- LOL, LOS, FOS alarm outputs
- Digitally-controlled output phase
- Integrated loop filter with selectable adjustment
- I2C or SPI programmable
- Meets OC-192 GR-253-CORE jitter
- Dual clock inputs with manual or