SI5326 Datasheet | Silicon Labs

Features - Generates any frequency from 2 k Hz - Dual clock outputs with selectable to 945 MHz and select frequencies to signal format 1.4 GHz from an input frequency of - Support for ITU G.709 and custom 2 k Hz to 710 MHz FEC ratios (255/238, 255/237, - Ultra-low jitter clock outputs with jitter 255/236) generation as low as 0.3 ps rms - LOL, LOS, FOS alarm outputs (50 k Hz- 80 MHz) - Digitally-controlled output phase - Integrated loop filter with selectable adjustment loop bandwidth (60 Hz to 8.4 k Hz) - I2C or SPI programmable - Meets OC-192 GR-253-CORE jitter - On-chip voltage regulator for specifications 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10% - Dual clock inputs with manual or operation automatically controlled hitless - Small size: 6 x 6 mm 36-lead QFN switching (LVPECL, LVDS, CML, - Pb-free, ROHS pliant CMOS) Applications - SONET/SDH OC-48/OC-192/STM- - Optical modules 16/STM-64 line cards - Wireless basestations - ITU G.709 and custom FEC line - Data converter clocking cards - x DSL - Gb E/10Gb E, 1/2/4/8/10G Fibre - PDH clock synthesis Channel line cards - Test and measurement - Gb E/10Gb E Synchronous Ethernet - Broadcast video Description The Si5326 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance. The Si5326 accepts two input clocks ranging from 2 k Hz to 710 MHz and generates two output clocks ranging from 2 k Hz to 945 MHz and select frequencies to 1.4 GHz. The two outputs are divided down separately from a mon source. The Si5326 can also use its crystal oscillator as a clock source for frequency synthesis. The device provides virtually any frequency translation bination across this operating range. The Si5326 input clock frequency and clock multiplication ratio are programmable through an I2C or SPI interface. The Si5326 is based on Silicon Laboratories' 3rd-generation DSPLL® technology, which provides frequency synthesis and jitter attenuation in a highly integrated PLL solution...