SI5327 Datasheet | Silicon Labs

Features - Generates any frequency from 2 k Hz - Dual clock inputs with manually to 808 MHz from an input frequency controlled hitless switching of 2 k Hz to 710 MHz - Free run and VCO freeze modes - Ultra-low jitter clock outputs with jitter - Support for ITU G.709 and custom generation as low as 0.5 ps rms FEC ratios (255/238, 255/237, (12 k Hz- 20 MHz) 255/236) - Integrated loop filter with selectable - LOL and LOS alarm outputs loop bandwidth (4 to 525 Hz) - I2C or SPI programmable - Meets OC-192 GR-253-CORE jitter - Single 1.8, 2.5, 3.3 V supply specifications - Small size: 6 x 6 mm 36-lead QFN - Pb-free, ROHS pliant Applications - Dual clock outputs with - Synchronous Ethernet programmable signal format - Optical modules (LVPECL, LVDS, CML, CMOS) - Wireless repeaters/ - SONET/SDH OC-48/OC-192/STM- wireless backhaul 16/STM-64 line cards - Data converter clocking - ITU G.709 and custom FEC line - x DSL cards - PDH clock synthesis - Gb E/10Gb E, 1/2/4/8/10G Fibre - Test and measurement Channel line cards - Broadcast video Description The Si5327 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance. The Si5327 accepts two input clocks ranging from 2 k Hz to 710 MHz and generates two output clocks ranging from 2 k Hz to 808 MHz. The two outputs are divided down separately from a mon source. The Si5327 can also use its crystal oscillator as a clock source for frequency synthesis. The device provides virtually any frequency translation bination across this operating range. The Si5327 input clock frequency and clock multiplication ratio are programmable through an I2C or SPI interface. The Si5327 is based on Silicon Laboratories' 3rd-generation DSPLL® technology, which provides frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter ponents. The DSPLL loop bandwidth is digitally programmable, providing jitter...