SI5330
Overview
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- Supports single-ended or differential input clock signals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs Provides signal level translation
- Differential to single-ended
- Single-ended to differential
- Differential to differential
- Single-ended to single-ended Wide frequency range
- LVPECL, LVDS: 5 to 710 MHz
- HCSL: 5 to 250 MHz
- SSTL, HSTL: 5 to 350 MHz
- CMOS: 5 to 200 MHz Additive jitter: 150 fs RMS typ * * * * * * *
