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SI5330 - LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR

General Description

.

.9 3.1.

.9 3.2.

Key Features

  • 18 17 16 15 14 13 7 8 9 10 11 12.
  • Supports single-ended or differential input clock signals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs Provides signal level translation.
  • Differential to single-ended.
  • Single-ended to differential.
  • Differential to differential.
  • Single-ended to single-ended Wide frequency range.
  • LVPECL, LVDS: 5 to 710 MHz.
  • HCSL: 5 to 250 MHz.
  • SSTL, HSTL: 5 to.

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Other Datasheets by Silicon Laboratories

Part Number Description
SI53301 1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR
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SI53303 DUAL 1:5 LOW JITTER BUFFER/LEVEL TRANSLATOR
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SI53305 1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Si5330 1 . 8 / 2 . 5 / 3 .