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CXK77V3211Q -12/14
32768-word by 32-bit High Speed Synchronous Static RAM
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Description The CXK77V3211Q is a 32K × 32 high performance synchronous SRAM with a 2-bit burst counter and output register. All synchronous inputs pass through register controlled by a positive-edge-triggered single clock input (CLK). The synchronous inputs include all addresses, all data inputs, chip enable (CE), two additional chip enables for easy depth expansion (CE2, CE2), burst control inputs (ADSC, ADSP, ADV), four individual byte write enables (BW1, BW2, BW3, BW4), one byte write enable (BWE), and global write enable (SGW). Asynchronous inputs include the output enable (OE) and power down control (ZZ).