ST3421SRG Datasheet | Stanson Technology

DESCRIPTION ST3421SRG is the P-Channel logic enhancement mode power field effect transistor which is produced using high cell density, DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage application such as cellular phone and notebook puter power management, other battery powered circuits, and low in-line power loss are required. The product is in a very small outline surface mount package. PIN CONFIGURATION SOT-23 3 D G 1 S 2 FEATURE -60V/-5.0A, RDS(ON) = 150m-ohm (Typ.) @VGS = -10V -60V/-2.5A, RDS(ON) = 185m-ohm @VGS = -4.5V Super high density cell design for extremely low RDS(ON) Exceptional on-resistance and maximum DC current capability SOT-23 package design 1.Gate 2.Source 3.Drain PART MARKING SOT-23 21YA 12 Y: Year Code A: Process Code STANSON TECHNOLOGY 120 Bentley Square, Mountain View, Ca 94040 USA .stansontech. ST3421SRG 2013. Rev.1 P Channel Enhancement Mode MOSFET -5.0A ABSOULTE MAXIMUM RATINGS (Ta = 25℃ Unless otherwise noted ) Parameter Symbol Typical Drain-Source Voltage Gate-Source Voltage Continuous Drain Current TJ=150℃) TA=25℃ TA=70℃ Pulsed Drain Current VDSS VGSS ID IDM -60 ±20 -5.0 -3.5 -12 Continuous Source Current (Diode Conduction) Power Dissipation TA=25℃ TA=70℃ Operation Junction Temperature IS PD TJ -1.25 1.25 0.8 Storgae Temperature...