ST3424 Datasheet | Stanson Technology

DESCRIPTION The ST3424 is the N-Channel logic enhancement mode power field effect transistor is produced using high cell density, DMOS trench technology. This high-density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage application such as cellular phone and notebook puter power management and other battery powered circuits where high side switching. PIN CONFIGURATION SOT-23 FEATURE l- 60V/4.0A, RDS(ON) = 55mΩ @VGS = 10V l- 60V/3.0A, RDS(ON) = 60mΩ @VGS = 4.5V l- Super high density cell design for extremely low RDS(ON) l- Exceptional on-resistance and maximum DC current capability l- SOT-23 package design 1.Gate 2.Source 3.Drain PART MARKING SOT-23 24YA 12 Y: Year Code A: Process Code 120 Bentley Square, Mountain View, Ca 94040 USA http://.stnasontech. STN3424 2014. V1 N Channel Enhancement Mode MOSFET 4.0A ABSOULTE MAXIMUM RATINGS (Ta = 25℃ Unless otherwise noted ) Parameter Symbol Typical Drain-Source Voltage Gate-Source Voltage Continuous Drain Current TJ=150℃) TA=25℃ TA=70℃ Pulsed Drain Current VDSS VGSS ID IDM ±20 4.0 2.6 26 Continuous Source Current (Diode Conduction) Power Dissipation TA=25℃ TA=70℃ 1.8 1.0 Operation Junction Temperature TJ -55/150 Storgae Temperature Range TSTG -55/150 Thermal Resistance-Junction to...