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THC63LVDM63A - (THC63LVDF64A / THC63LVDM63A) LVDS 18-Bit Color Host-LCD Panel Interface Receiver

This page provides the datasheet information for the THC63LVDM63A, a member of the THC63LVDF64A (THC63LVDF64A / THC63LVDM63A) LVDS 18-Bit Color Host-LCD Panel Interface Receiver family.

Datasheet Summary

Description

The THC63LVDM63A transmitter converts 21 bits of CMOS/TTL data into LVDS(Low Voltage Differential Signaling) data stream.

A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link.

Features

  • 21:3 Data channel compression at up to 223 Megabytes per sec throughput Wide Frequency Range: 20 - 85 MHz suited for VGA,SVGA,XGA and SXGA Narrow bus (8 lines) reduces cable size 345mV swing LVDS devices for Low EMI Supports Spread Spectrum Clock Generator On chip Input Jitter Filtering PLL requires No External Components Single 3.3V supply with 110mW(TYP) Low Power CMOS Design Power-Down Mode Low profile 48 Lead TSSOP Package Clock Edge Programmable for Transmitter Improved Replacement for the.

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Datasheet Details

Part number THC63LVDM63A
Manufacturer THine Electronics
File Size 75.96 KB
Description (THC63LVDF64A / THC63LVDM63A) LVDS 18-Bit Color Host-LCD Panel Interface Receiver
Datasheet download datasheet THC63LVDM63A Datasheet
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Other Datasheets by THine Electronics
  • THC63LVDM63R - (THC63LVDM63R / THC63LVDM83R) Reduced Swing LVDS 24-Bit / 18-Bit Color Host LCD Panel Interface
  • THC63LVDM83C - REDUCED SWING LVDS 24Bit COLOR HOST-LCD PANEL INTERFACE
  • THC63LVDM83D - 24bit COLOR LVDS TRANSMITTER
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  • THC63LVD103 - 135MHz 30Bits COLOR LVDS Transmitter
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Full PDF Text Transcription

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www.DataSheet4U.com Version 2.10 THine THC63LVDM63A/THC63LVDF64A PRELIMINARY 85MHz LVDS 18 Bit COLOR HOST-LCD PANEL INTERFACE General Description The THC63LVDM63A transmitter converts 21 bits of CMOS/TTL data into LVDS(Low Voltage Differential Signaling) data stream. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. The THC63LVDM63A can be programmed for rising edge or falling edge clocks through a dedicated pin. The THC63LVDF64A receiver convert the LVDS data streams back into 21 bits of CMOS/TTL data with falling edge clock. At a transmit clock frequency of 85MHz, 18 bits of RGB data and 3 bits of LCD timing and control data (HSYNC, VSYNC, CNTL1) are transmitted at a rate of 595 Mbps per LVDS data channel.
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