Download the THC63LVDM63A datasheet PDF.
This datasheet also covers the THC63LVDF64A variant, as both devices belong to the same (thc63lvdf64a / thc63lvdm63a) lvds 18-bit color host-lcd panel interface receiver family and are provided as variant models within a single manufacturer datasheet.
General Description
The THC63LVDM63A transmitter converts 21 bits of CMOS/TTL data into LVDS(Low Voltage Differential Signaling) data stream.
A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link.
Key Features
21:3 Data channel compression at up to 223 Megabytes per sec throughput Wide Frequency Range: 20 - 85 MHz suited for VGA,SVGA,XGA and SXGA Narrow bus (8 lines) reduces cable size 345mV swing LVDS devices for Low EMI Supports Spread Spectrum Clock Generator On chip Input Jitter Filtering PLL requires No External Components Single 3.3V supply with 110mW(TYP) Low Power CMOS Design Power-Down Mode Low profile 48 Lead TSSOP Package Clock Edge Programmable for Transmitter Improved Replacement for the.
Note: The manufacturer provides a single datasheet file (THC63LVDF64A_THineElectronics.pdf) that lists specifications for multiple related part numbers.
Datasheet Details
Part number
THC63LVDM63A
Manufacturer
THine Electronics
File Size
75.96 KB
Description
(THC63LVDF64A / THC63LVDM63A) LVDS 18-Bit Color Host-LCD Panel Interface Receiver
Full PDF Text Transcription for THC63LVDM63A (Reference)
Note: Below is a high-fidelity text extraction (approx. 800 characters) for
THC63LVDM63A. For precise diagrams, and layout, please refer to the original PDF.
www.DataSheet4U.com Version 2.10 THine THC63LVDM63A/THC63LVDF64A PRELIMINARY 85MHz LVDS 18 Bit COLOR HOST-LCD PANEL INTERFACE General Description The THC63LVDM63A transmi...
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HOST-LCD PANEL INTERFACE General Description The THC63LVDM63A transmitter converts 21 bits of CMOS/TTL data into LVDS(Low Voltage Differential Signaling) data stream. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. The THC63LVDM63A can be programmed for rising edge or falling edge clocks through a dedicated pin. The THC63LVDF64A receiver convert the LVDS data streams back into 21 bits of CMOS/TTL data with falling edge clock. At a transmit clock frequency of 85MHz, 18 bits of RGB data and 3 bits of LCD timing and control data (HSYNC, VSYNC, CNTL1) are transmitted at
THC63LVDM63A Datasheet
