THC63LVDM63R Datasheet | THine Electronics

Description The THC63LVDM83R transmitter converts 28bits of CMOS/TTL data into LVDS (Low Voltage Differential Signaling) data stream. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. At a transmit clock frequency of 85MHz, 28bits of RGB data and 4bits of LCD timing and control data (HSYNC, VSYNC, CNTL1, CNTL2) are transmitted at a rate of 595Mbps per LVDS channel. Also available is THC63LVDM63R that converts 21bits of CMOS/TTL data into LVDS(Low Voltage Differential Signaling) data stream. Both transmitters can be programmed reduced swing LVDS through a dedicated pin for low power consumption and EMI. Features - 28:4 Data channel pression at up to 298 Megabytes per sec throughput - Wide dot clock range: 20-85MHz suited for VGA, - - Support Reduced swing LVDS for Low EMI - 200m V swing LVDS/350m V swing LVDS - - - - - - - - selectable Support Spread Spectrum Clock Generator On chip Input Jitter Filtering PLL requires No external ponents Single 3.3V supply with 125m W(TYP) Power-Down Mode Low profile 56 or 48 Lead TSSOP Package SVGA, XGA and SXGA Narrow bus (10 lines or 8 lines) reduces cable size Clock Edge Programmable Improved Replacement for the National DS90C383 or DS90C363 . Block Diagram Data Shee CMOS/TTL INPUTS TA0-6 TB0-6 TC0-6 TD0-6 7 7 7 7 THC63LVDM83R DATA (LVDS) TA +/TB +/TC +/TD +/(140-595Mbit/On Each LVDS Channel) CMOS/TTL INPUTS TA0-6 TB0-6 TC0-6 7 7 7 DATA (LVDS) TA +/TB +/TC +/- TTL PARALLEL TO SERIAL TTL PARALLEL TO SERIAL TRANSMITTER CLOCK IN (20 to 85MHz) R/F /PDWN RS (140-595Mbit/On Each LVDS Channel) TRANSMITTER CLOCK IN (20 to 85MHz) R/F /PDWN RS PLL TCLK +/CLOCK (LVDS) 20-85MHz TCLK +/CLOCK (LVDS) 20-85MHz . Copyright 2001-2003 THine Electronics, Inc. All rights reserved 1 THine Electronics, Inc. . Data Sheet 4 U . .. THC63LVDM83R /THC63LVDM63R_Rev2.0 Pin Out THC63LVDM83R THC63LVDM63R RS TD1 TA5 TA6 GND TB0 TB1 TD2 VCC TD3 TB2 TB3 GND TB4 TB5 TD4 R/F TD5...