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tm TE CH
SDRAM
FEATURES
• 3.3V power supply • Clock cycle time : 6 / 7 / 8 / 10 ns • Dual banks operation • LVTTL compatible with multiplexed address • All inputs are sampled at the positive going
edge of system clock • Burst Read Single-bit Write operation • DQM for masking • Auto refresh and self refresh • 32ms refresh period (2K cycle) • MRS cycle with address key programs
- CAS Latency ( 2 & 3 ) - Burst Length ( 1 , 2 , 4 , 8 & full page) - Burst Type (Sequential & Interleave) • Available package type in 50 pin TSOP(II) and 60-pin CSP.