T431616B Datasheet | TMT

tm - - - - - - - - - TE CH SDRAM Features +2.7 to +3.6V power supply Dual banks operation LVTTL patible with multiplexed address All inputs are sampled at the positive going edge of system clock Burst Read Single-bit Write operation DQM for masking Auto refresh and self refresh 32ms refresh period (2K cycle) MRS cycle with address key programs - CAS Latency ( 1 & 2 & 3 ) - Burst Length ( 1 , 2 , 4 , 8 & full page) - Burst Type (Sequential & Interleave) Available package type in 50 pin TSOP(II) 1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM GRNERAL DESCRIPTION The T431616B is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 x 524,288 words by 16...