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TC55NEM216ASTV55 - (TC55NEM216ASTV55 / TC55NEM216ASTV77) MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

General Description

The TC55NEM216ASTV is a 4,194,304-bit static random access memory (SRAM) organized as 262,144 words by 16 bits.

Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 2.7 to 5.5 V power supply.

Key Features

  • Low-power dissipation Operating: 15 mW/MHz (typical) Single power supply voltage of 2.7 to 5.5 V Power down features using CE Data retention supply voltage of 2.0 to 5.5 V Direct TTL compatibility for all inputs and outputs Wide operating temperature range of.
  • 40° to 85°C Standby Current (maximum): 20 µA.
  • Access Times (maximum): TC55NEM216ASTV 55 Access Time CE Access Time OE Access Time 55 ns 55 ns 30 ns 7.

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Datasheet Details

Part number TC55NEM216ASTV55
Manufacturer Toshiba
File Size 159.27 KB
Description (TC55NEM216ASTV55 / TC55NEM216ASTV77) MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
Datasheet download datasheet TC55NEM216ASTV55 Datasheet

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Other Datasheets by Toshiba

Part Number Description
TC55NEM216ASTV77 (TC55NEM216ASTV55 / TC55NEM216ASTV77) MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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TC55NEM216ASTV55,70 www.DataSheet4U.com TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 262,144-WORD BY 16-BIT FULL CMOS STATIC RAM DESCRIPTION The TC55NEM216ASTV is a 4,194,304-bit static random access memory (SRAM) organized as 262,144 words by 16 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 2.7 to 5.5 V power supply. Advanced circuit technology provides both high speed and low power at an operating current of 3 mA/MHz (typ) and a minimum cycle time of 55 ns. It is automatically placed in low-power mode at 1 µA standby current (typ) when chip enable ( CE ) is asserted high or chip select (CS) is asserted low. There are three control inputs.