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TH58100FT - TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

General Description

The TH58100 is a single 3.3 V 1-Gbit (1,107,296,256) bit NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as 528 bytes ´ 32 pages ´ 8192 blocks.

Key Features

  • Organization Memory cell allay 528 ´ 128K ´ 8 ´ 2 Register 528 ´ 8 Page size 528 bytes Block size (16K + 512) bytes Modes Read, Reset, Auto Page Program Auto Block Erase, Status Read Multi Block Program, Multi Block Erase Mode control Serial input/output Command control.
  • Power supply VCC = 2.7 V to 3.6 V Program/Erase Cycles 1E5 cycle (with ECC) Access time Cell array to register 25 ms max Serial Read Cycle 50 ns min Operating current Read (50 ns cycle) 10 mA typ. Pr.

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Datasheet Details

Part number TH58100FT
Manufacturer Toshiba
File Size 421.77 KB
Description TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
Datasheet download datasheet TH58100FT Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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TH58100FT TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 2 1-GBIT (128M ´ 8 BITS) CMOS NAND E PROM DESCRIPTION The TH58100 is a single 3.3 V 1-Gbit (1,107,296,256) bit NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as 528 bytes ´ 32 pages ´ 8192 blocks. The device has a 528-byte static register which allows program and read data to be transferred between the register and the memory cell array in 528-byte increments. The Erase operation is implemented in a single block unit (16 Kbytes + 512 bytes: 528 bytes ´ 32 pages). The TH58100 is a serial-type memory device which utilizes the I/O pins for both address and data input/output as well as for command inputs.