TH58100FTI - TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

Product Overview

Toshiba Semiconductor

Datasheet Details

Part number	TH58100FTI
Manufacturer	Toshiba Semiconductor
File Size	495.96 KB
Description	TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
Datasheet	TH58100FTI Datasheet
Additional preview pages of the TH58100FTI datasheet.

Product details

Description

The TH58100 is a single 3.3 V 1-Gbit (1,107,296,256) bit NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as 528 bytes × 32 pages × 8192 blocks.

Features

Organization Memory cell allay 528 × 128K × 8 × 2 Register 528 × 8 Page size 528 bytes Block size (16K + 512) bytes Modes Read, Reset, Auto Page Program Auto Block Erase, Status Read Multi Block Program, Multi Block Erase Mode control Serial input/output Command control.
Power supply VCC = 2.7 V to 3.6 V Program/Erase Cycles 1E5 cycle (with ECC) Access time Cell array to register 25 µs max Serial Read Cycle 50 ns min Operating current Read (50 ns.

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Published: Dec 21, 2005 |