TH58100FTI Datasheet PDF - Toshiba Semiconductor TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS Specs

TH58100FTI - TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

Datasheet Summary

Description

The TH58100 is a single 3.3 V 1-Gbit (1,107,296,256) bit NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as 528 bytes × 32 pages × 8192 blocks.

Features

Organization Memory cell allay 528 × 128K × 8 × 2 Register 528 × 8 Page size 528 bytes Block size (16K + 512) bytes Modes Read, Reset, Auto Page Program Auto Block Erase, Status Read Multi Block Program, Multi Block Erase Mode control Serial input/output Command control.
Power supply VCC = 2.7 V to 3.6 V Program/Erase Cycles 1E5 cycle (with ECC) Access time Cell array to register 25 µs max Serial Read Cycle 50 ns min Operating current Read (50 ns.

Datasheet Details

Part number	TH58100FTI
Manufacturer	Toshiba Semiconductor
File Size	495.96 KB
Description	TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
Datasheet	TH58100FTI Datasheet
Additional preview pages of the TH58100FTI datasheet.

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Full PDF Text Transcription

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TH58100FTI TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 2 1-GBIT (128M × 8 BITS) CMOS NAND E PROM DESCRIPTION The TH58100 is a single 3.3 V 1-Gbit (1,107,296,256) bit NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as 528 bytes × 32 pages × 8192 blocks. The device has a 528-byte static register which allows program and read data to be transferred between the register and the memory cell array in 528-byte increments. The Erase operation is implemented in a single block unit (16 Kbytes + 512 bytes: 528 bytes × 32 pages). The TH58100 is a serial-type memory device which utilizes the I/O pins for both address and data input/output as well as for command inputs.

Published: Dec 21, 2005 |